$ whoami bjwanneng — Creator
@bjwanneng
veriflow-cc · v1.0.0
Claude Code-driven RTL design pipeline — zero Python dependencies, Claude Code main session is the driver.
verilog-generator · v1.0.0
Generates a single synthesizable Verilog module from a natural language description or interface definition. Applies strict Verilog-2005 coding rules, AXI-Stream handshake validation, and optional user-supplied coding style (Markdown rule f
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